Three dimensional (3D) integrated circuit stacking has gained popularity as an integration scheme over conventional two dimensional processes in recent years as it offers benefits such as small footprint and improved performance. For example, 3D integrated circuit stacking involves stacking semiconductor wafers and/or dies, and interconnecting them vertically using vias, such as through substrate vias (TSVs). The 3D stacking of complementary bipolar complementary-metal-oxide semiconductor (BiCMOS), mixed-signal/CMOS, radio frequency (“RF”) CMOS, and CMOS image sensor technologies formed on semiconductor dies and/or wafers requires a large number of via connections at different levels. In imaging applications, for example, every pixel in an imaging array needs at least one via for making an electrical connection. Thus, it is important for TSVs to have reduced pitches and high aspect ratios.
A conventional method of forming a TSV involves etching a hole in a substrate, lining the sidewalls of the hole with an isolation material, and filling the hole with a conductive material. Since the substrate may include several layers, etching a hole through different layers of the substrate may require different etching chemistries and/or methods. As a result, TSVs formed using the conventional method typically have a critical dimension (CD) width of at least 10 microns (i.e., 10*10−6 meters). Also, a pitch, which is the separation between the middle of one TSV and the middle of an adjacent TSV, is typically 10 microns or larger. TSVs with large pitches and low aspect ratios require semiconductor dies with large footprints, which may be undesirable for certain applications.
Thus, there is a need in the art for a structure having substrate vias with decreased pitch and increased aspect ratio.